Competition in the electronics industry is currently being driven by a continual need for smaller components and devices. Miniaturization will likely remain a fundamental driving force for the electronics industry for the foreseeable future. In order to meet the requirement for continually smaller electronic components on packages such as printed wiring boards and laminated chip carriers, it will be necessary to develop printed circuit fabrication techniques which allow narrower circuit patterns and higher resolution.
Typically, manufacturers employ three technologies for fabrication of printed wiring boards. These include the many varieties of subtractive, semi-additive, and full additive processes for fabricating fine-line circuitry on printed wiring boards. Each of these processes has known difficulties and limitations with regard to producing high quality, high density, fine-line circuitry.
A conventional subtractive process requires that a full panel plating of copper be employed followed by imaging and developing of an overcoated resist layer, followed by etching of the copper in areas where the resist was removed. Major problems associated with this process include the fact that large amounts of copper must be etched away and that it is common for undercutting of the remaining circuitry to occur, especially the well known galvanic etching in areas where noble metals are present in proximity to the copper circuitry. There is also a problem of insufficient resolution using the subtractive process. This significantly limits the ultimate density of the fine-line circuitry. For example, it is well known that as the line or space dimension approaches the thickness of the layer to be etched, subtractive etching becomes unacceptable. To remedy this situation, the etch mask must be made larger than the desired feature to allow for this lateral etching.
To circumvent problems associated with the subtractive process, additive processes have been employed. However, problems are encountered with the need for an adhesion promoting seed layer that must be applied after a photoresist layer is imaged. This seed layer covers not only the desired areas to be plated but also covers the top surfaces of the photoresist layer. This can cause copper to be plated in areas where copper plating is not desired. To circumvent this problem, the photoresist must be chemically or mechanically cleaned of the seed layer. Mechanical etching of the seed layer is known to cause physical defects in the final product due to minute particles causing conductive junctions between what should have been discrete circuit lines. Another potential defect caused by mechanical cleaning is that stress placed on the microcomponent can potentially cause delamination. Also, the process is relatively expensive due to the required build-up of copper microcircuitry during electroless plating.
To address problems associated with both the additive and subtractive processes, a semi-additive process has been utilized. A typical semi-additive process involves laminating a thin layer of copper to a substrate, coating the thin layer of copper with a resist layer, imaging and developing the resist layer to expose selected portions of the underlying thin copper layer, electroplating the exposed areas of the thin copper layer, removing the remaining photoresist, and etching the uncovered thin copper layer to create discrete microcomponent features. The minimum thickness of the copper foil that can be applied in the semi-additive process is limited by handling problems during the lamination process, and this minimum thickness is larger than would be desired in order to create extremely fine line features.
In order to provide electrical continuity between opposite sides of a substrate having printed circuitry on both sides, metallized through-holes or vias are provided in printed wiring boards. The predominant method for metallization of through-holes or vias is by electroless copper plating followed by electroplating. This process uses as many as 8 separate steps involving as many as 17 processing tanks. The process uses chelated copper cations in solution and formaldehyde as a reducing agent. The formaldehyde is toxic and is being legislated out of use, while the waste treatment and recovery of chelated copper cations is particularly difficult. Further, adhesion of electroless copper to a glass/epoxy core of FR-4 laminates is a challenging problem, especially under increasingly stringent thermal cycling testing. There are alternative electroless plating processes on the market, but these processes cannot meet the testing requirement for adhesion in thermal cycling in flex-rigid boards for certain military and other applications.
Accordingly, there is a need for improved processes for selectively depositing an electrically conductive material on a dielectric substrate. In particular, an additive process for fabricating fine-line circuitry on printed wiring boards which overcomes the problems associated with conventional additive, subtractive and semi-additive processes would be desirable. Further, improved processes for metallization of the walls of through-holes or vias in printed wiring boards, which eliminate problems associated with electroless plating, would be highly desirable.